Title :
A receiver architecture for intra-band carrier aggregation
Author :
Sy-Chyuan Hwu ; Razavi, Behzad
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A block downconversion receiver incorporates a digital image rejection technique to support multiple aggregated carriers by one receive path and one frequency synthesizer. A prototype consisting of a CMOS RF front end and an FPGA back end exhibits an image rejection ratio (IRR) of at least 70 dB across 2 GHz ± 25 MHz and reconstructs a -76-dBm 64-QAM signal with an EVM of -30 dB in the presence of another channel 40 dB higher.
Keywords :
CMOS integrated circuits; field programmable gate arrays; quadrature amplitude modulation; radio receivers; radiofrequency integrated circuits; 64-QAM signal; CMOS RF front end; EVM; FPGA back end; IRR; block downconversion receiver; digital image rejection technique; frequency synthesizer; image rejection ratio; intra-band carrier aggregation; multiple aggregated carriers; receiver architecture; Logic gates; Mixers; Radio frequency; Standards;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858418
