A Dual-Vt low leakage SRAM array robust to process variations

This paper presents a dual-V_t SRAM array design which is robust to process variations. After reviewing a cell-level analysis to compare various dual-V_t configurations under variations, an algorithm is introduced which assigns a configuration to each cell in an SRAM array to meet a target read delay with minimum leakage at a desired probability. Two versions of the algorithm are discussed which trade off accuracy in wire delay estimation with granularity of assignment. Simulation results show the probability of meeting a target read delay at various locations is at least 0.93 using our proposed techniques.