Title :
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications
Author :
Chang-Hung Tsai ; Tung-Yu Wu ; Shu-Yu Hsu ; Chia-Ching Chu ; Fang-Ju Ku ; Ying-Siou Laio ; Chih-Lung Chen ; Wing-Hung Wong ; Hsie-Chia Chang ; Chen-Yi Lee
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D2MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.
Keywords :
Big Data; CMOS integrated circuits; data analysis; learning (artificial intelligence); query processing; 3-layer dimension merging; Big Data analysis; CMOS technology; CPU; D2MLP; GPGPU; MIMD architecture; configurable counting engine array; data-driven machine learning processor; energy-efficient solution; frequency 165 MHz; learned density model; maximal 1-128/1024 dimensional data; parallel 64/8 queries; size 90 nm; voltage 1.0 V; Big data; Computational modeling; Computer architecture; Data models; Engines; Filtering; Merging;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858422
