A portless SRAM Cell using stunted wordline drivers

A minimum area portless SRAM cell is presented along with a stunted wordline driver. When compared to an iso-area 6T cell using logic design rules, the portless cell exhibits 22% higher static noise margin and 14% lower leakage with a 51% penalty in the on/off cell current ratio. Measurements from a fabricated test chip in 0.5 mum CMOS demonstrate functionality of the proposed cell and driver in an array, and for the first time, validate the portless concept in an isolated test cell.