Title :
A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications
Author :
Ju, Chi-Cheng ; Liu, Tsu-Ming ; Chang, Yung-Chang ; Wang, Chih-Ming ; Lin, Hue-Min ; Cheng, Subrina ; Chun-Chia Chen ; Chiu, Fred ; Lin, Kung-Sheng ; Wu, Chung-Bin ; Liang, Sling ; Wang, Sheng-Jen ; Chen, Ginny ; Hsiao, TC ; Wang, Chi-Hui
Author_Institution :
Mediatek Inc., Hsinchu
Abstract :
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.
Keywords :
CMOS memory circuits; SRAM chips; decoding; image sequences; logic gates; video coding; Blu-ray Disc player; clock frequency; embedded SRAM; frequency 200 MHz; fully-compliant high-definition video decoder LSI; high-definition sequences; logic gates; memory management; power 317 mW; power dissipation; resource sharing; single-poly seven-metal CMOS process; size 90 micron; voltage 1 V; CMOS logic circuits; Decoding; High definition video; Large scale integration; Logic gates; Logic testing; Memory management; Resource management; Throughput; Video sharing;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708716
