Title :
Presetting pulse-based flip-flop
Author :
Kim, Chul-Soo ; Kim, Joo-Seong ; Kong, Bai-Sun ; Moon, Yongsam ; Jun, Young-Hyun
Author_Institution :
Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon
Abstract :
In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip- flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.
Keywords :
CMOS integrated circuits; flip-flops; pulse circuits; CMOS process; clock-skew tolerance; data-to-output delay; power-delay product; presetting pulse-based flip-flop; Clocks; Delay effects; Design engineering; Energy consumption; Flip-flops; Latches; Medium voltage; Moon; Random access memory; Sampling methods;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541486
