Title :
A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS
Author :
Gerosa, Gianfranco ; Curtis, Steve ; Addeo, Mike D. ; Jiang, Bo ; Kuttanna, Belliappa ; Merchant, Feroze ; Patel, Binta ; Taufique, Mohammed ; Samarchi, Haytham
Author_Institution :
Intel Corp., Austin, TX
Abstract :
This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz.
Keywords :
CMOS integrated circuits; Internet; cache storage; instruction sets; low-power electronics; microprocessor chips; mobile radio; pipeline processing; CMOS process; Hi-K metal gate CMOS; IA processor design; L2 cache; die size; dual-mode front-side-bus; floating point execution units; frequency 1.86 GHz; front-side-bus; in-order pipeline; low power Intel architecture processor; mobile internet device; power 2 W; size 45 nm; storage capacity 24 Kbit; storage capacity 32 Kbit; storage capacity 512 Kbit; synthetic power-virus test; temperature 90 C; thermal design power consumption; transistors; voltage 1.0 V; CMOS process; Frequency; Hardware; Internet; Job shop scheduling; Pipelines; Power measurement; Process design; Testing; Yarn;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708718
