DocumentCode :
183175
Title :
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range
Author :
Bol, David ; de Streel, Guerric ; Botman, Francois ; Lusala, Angelo Kuti ; Couniot, Numa
Author_Institution :
ICTEAM Inst., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
fYear :
2014
fDate :
10-13 June 2014
Firstpage :
1
Lastpage :
2
Abstract :
We propose a CMOS image sensor operating at ultra-low voltage (ULV) in a 65-nm low-power (LP) CMOS logic process for ultra-low-power SoC integration. Energy of 17-pJ/frame.pixel and 4×4-μm pixel size with 57-% fill factor are achieved at 0.5 V with digital pixel sensor (DPS) and time-based readout while reaching 40-dB dynamic range (DR) despite high leakage currents and Vt variability, thanks to delta-reset sampling (DRS) as well as gating and adaptive body biasing (ABB) of the 2-transistor (2-T) in-pixel comparator.
Keywords :
CMOS image sensors; CMOS logic circuits; leakage currents; low-power electronics; system-on-chip; 2-T in-pixel comparator; 2-transistor in-pixel comparator; ABB; DPS; DPS CMOS image sensor; DR; DRS; LP CMOS logic process; ULV; adaptive body biasing; delta-reset sampling; digital pixel sensor; dynamic range; fill factor; high leakage currents; low-power CMOS logic process; size 65 nm; threshold voltage variability; time-based readout; ultra-low voltage; ultra-low-power SoC integration; voltage 0.5 V; CMOS integrated circuits; Clocks; Dark current; Monitoring; System-on-chip; Wireless communication; Wireless sensor networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
Type :
conf
DOI :
10.1109/VLSIC.2014.6858426
Filename :
6858426
Link To Document :
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