Title :
A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation
Author :
Yeager, Doug ; Biederman, William ; Narevsky, Nathan ; Leverett, Jaclyn ; Neely, Ryan ; Carmena, Jose M ; Alon, Elad ; Rabaey, Jan M.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California Berkeley, Berkeley, CA, USA
Abstract :
A 65nm CMOS 4.78mm2 integrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.
Keywords :
CMOS digital integrated circuits; data compression; neural chips; system-on-chip; CMOS integrated neuromodulation SoC; acquisition channels; current 150 muA; digital compression; epoch compression; frequency 100 Hz; frequency 50 Hz; fully-integrated neuromodulation SoC; power 417 muW; simultaneous dual stimulation; size 65 nm; voltage 1.2 V; Abstracts; Data mining; Electrodes; Firing; Noise;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858430
