Title :
Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application
Author :
Chung, Hoeju ; Jang, Youngchan ; Choi, Youngdon ; Park, Hwanwook ; Kim, Jaekwan ; Lim, Soouk ; Sunwoo, Jung ; Park, Moonsook ; Kim, Hyungwsuk ; Kim, Sang-Yun ; Kim, Hyun-Kyung ; Chung, Su-Jin ; Lee, Eun-Mi ; Kim, Youngju ; Lee, Yun-Sang ; Kim, Woo-Seop ;
Author_Institution :
ATD Team, Samsung Electron. Co., Ltd., Hwasung
Abstract :
A 5.8 Gb/s/pin DRAM with unidirectional differential I/Os and 1 Gbit memory core was designed and 23.2 GB/s memory module was assembled. Tx BER measurement on an electrical test board similar to real memory sub-systempsilas environment was performed and the results show that no additional coding for the differential I/O protection, like CRC, seems to be required up to 5.8 Gb/s/pin operation. Also, an efficient timing usage method using matched path for a possible implementation of CRC computation in ODIC architecture was proposed.
Keywords :
DRAM chips; cyclic redundancy check codes; encoding; error statistics; modules; CRC computation; DRAM application; ODIC architecture; byte rate 23.2 GByte/s; channel BER measurement; coding; electrical test board; memory core; memory module; unidirectional differential I/O; Assembly; Bit error rate; Computer architecture; Cyclic redundancy check; Electric variables measurement; Performance evaluation; Protection; Random access memory; Testing; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708721
