Title :
An 8mW 10b 50MS/s pipelined ADC using 25dB opamp
Author :
Kim, Min Gyu ; Kratyuk, Volodymyr ; Hanumolu, Pavan Kumar ; Ahn, Gil-Cho ; Kwon, Sunwoo ; Moon, Un-Ku
Author_Institution :
Broadcom Corp., Irvine, CA
Abstract :
In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; operational amplifiers; analog-to-digital converter; background offset calibration; gain 25 dB; intermediate gain stage; opamp; pipelined ADC; power 8 mW; reference scaling scheme; size 90 nm; voltage 1 V; CMOS technology; Calibration; Capacitors; Degradation; Linearity; Logic circuits; Logic design; Moon; Solid state circuit design; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708726
