Title :
Timing optimization of FPGA placements by logic replication
Author :
Beraudo, Giancarlo ; Lillis, John
Author_Institution :
ECE Dept., Univ. of Illinois, Chicago, IL, USA
Abstract :
Logic replication for placement level timing optimization is studied in the context of FPGAs. We make the observation that critical paths are dominated by interconnect delay and are frequently highly circuitous. We propose a systematic replication technique to "straighten" such paths. The resulting algorithm has several components: cell selection, slot selection for a duplicate cell, fanout partitioning and placement legalization. This algorithm is described and promising preliminary experimental results are reported with up to 29% improvement in critical path delay.
Keywords :
circuit optimisation; delay estimation; field programmable gate arrays; logic design; timing circuits; FPGA placement algorithm; cell selection; critical paths; fanout partitioning; interconnect delay; logic replication; placement legalization; slot selection; timing optimization; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic design; Partitioning algorithms; Permission; Programmable logic arrays; Programmable logic devices; Timing;
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
DOI :
10.1109/DAC.2003.1218957
