A UWB CMOS 0.13μm low-noise amplifier with dual loop negative feedback

A low-noise amplifier for ultra wide band (UWB) applications is presented. The use of a dual-loop negative feedback topology is advantageous, since it allows to achieve both impedance matching and a very low noise figure, and saves a lot of chip area as no bulky inductors are needed. A nullor and a resistive feedback network are employed, and the values of the feedback elements involved are defined in order to fulfill the noise-figure, input impedance and power-gain requirements for an UWB receiver. To ensure circuit stability, frequency compensation is done by means of a phantom zero and the addition of a transistor connected between input and output, thus realizing a multipath structure. The design targets UMC 0.13mufrac14m CMOS IC technology and operation from a 1.2-volt supply. From circuit simulations, the power gain of the LNA amounts to 17dB, and the bandwidth spans up to 12 GHz. Su is below -lOdB up to 10 GHz and the noise figure is below 3dB up to 8 GHz, and below 4dB@10 GHz. The power consumption equals 14 mA. Compared to competitive solutions, using resonating load stages or LC ladder networks, this chip will be much smaller and cheaper; it will use standard CMOS technology, and achieve very low noise, high gain and wide band matching at reasonable power consumption.