• DocumentCode
    183215
  • Title

    A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology

  • Author

    Sung-Jin Kim ; Taeik Kim ; Hojin Park

  • Author_Institution
    Samsung Electron., Yongin, South Korea
  • fYear
    2014
  • fDate
    10-13 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The first synchronous cyclic TDC is proposed in 28nm CMOS process. A novel 2x time amplifier whose gain is insensitive to variations and noise is proposed by using time conservative nature of the proposed synchronous time adder. The implemented 12b TDC occupies 0.01 mm2, consumes 820μW and it achieves 0.63ps of resolution over 2.6ns of input range.
  • Keywords
    CMOS integrated circuits; adders; amplifiers; integrated circuit noise; jitter; system-on-chip; time-digital conversion; 2x time amplifier; CMOS technology; SoC; first synchronous cyclic TDC; on-chip jitter measurement; power 820 muW; size 28 nm; storage capacity 12 bit; synchronous time adder; time 0.63 ps; Adders; Calibration; Clocks; Delays; Jitter; System-on-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits Digest of Technical Papers, 2014 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4799-3327-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2014.6858447
  • Filename
    6858447
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=183215