A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS

In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 times 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36 mm times 1.15 mm in 90 nm CMOS technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SR-TCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.