DocumentCode
183225
Title
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS
Author
Verbruggen, Bob ; Deguchi, Kenta ; Malki, Badr ; Craninckx, Jan
Author_Institution
IMEC, Leuven, Belgium
fYear
2014
fDate
10-13 June 2014
Firstpage
1
Lastpage
2
Abstract
We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
Keywords
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; calibration; integrated circuit noise; low-power electronics; SNDR; digital CMOS technology; dynamic pipelined SAR ADC; interleaved channel time-constant calibration; low power electronics; noise figure 70 dB; noise figure 70.7 dB; power 2.3 mW; residue amplifier; size 28 nm; voltage 0.9 V; word length 14 bit; CMOS integrated circuits; Calibration; Capacitors; Frequency measurement; Gain; Noise; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4799-3327-3
Type
conf
DOI
10.1109/VLSIC.2014.6858451
Filename
6858451
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