Title :
An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS
Author :
Inerfield, Mike ; Kamath, Anant ; Feng Su ; Hu, Jiankun ; Yu Xinyu ; Fong, Victor ; Alnaggar, Omar ; Fang Lin ; Kwan, T.
Author_Institution :
Broadcom Corp., San Jose, CA, USA
Abstract :
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power <; 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It uses a unique dual-reference, dual unit-cap architecture with a regulated DAC switch, providing a 2Vppd input swing while utilizing a low-voltage transistor implementation for the core ADC.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; CMOS process; core ADC; digital calibration circuitry; dual-reference SAR ADC architecture; dual-unit-cap architecture; low-voltage transistor implementation; power 8 mW; production quality; regulated DAC switch; sampling frequency; size 28 nm; voltage 2 V; voltage reference; Arrays; CMOS integrated circuits; Calibration; Capacitance; Capacitors; Noise; Switches; ADC; SAR;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858453
