A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration

Author

Yuan Zhou ; Benwei Xu ; Yun Chiu

Author_Institution

Univ. of Texas at Dallas, Dallas, TX, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 12b two-step pipelined SAR ADC reports a 66.7dB SNDR and an 86.9dB SFDR for a 5MHz sinusoidal input at 160MS/s. A digital background calibration based on opportunistic PN injection treats both DAC mismatch and residue-amplifier gain errors. The calibration enables a significant downsizing of the ADC input capacitance to yield a wideband, highly linear input network and an over-80dB SFDR while digitizing inputs from DC to 300MHz at full speed. The conversion FoM of this ADC is 20.7fJ/step at Nyquist. The prototype occupies an active area of 0.042mm² in a 40nm CMOS low-leakage digital process.

Keywords

CMOS digital integrated circuits; UHF amplifiers; UHF integrated circuits; VHF amplifiers; analogue-digital conversion; calibration; digital-analogue conversion; CMOS low-leakage digital process; DAC mismatch; FoM; frequency 300 MHz; frequency 5 MHz; input capacitance; noise figure 66.7 dB; noise figure 86.9 dB; opportunistic PN injection; opportunistic digital background calibration; residue-amplifier gain error; size 40 nm; storage capacity 12 bit; synchronous two-step pipelined SAR ADC; CMOS integrated circuits; Calibration; Capacitance; Clocks; Detectors; Prototypes; Time-domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858454

Filename

6858454