Architecture and implementation of Vulcan

Author

Stunkel, Craig B. ; Denneau, Monty M. ; Nathanson, Ben J. ; Shea, Dennis G. ; Hochschild, Peter H. ; Tsao, Michael ; Abali, Bülent ; Joseph, Douglas J. ; Varker, Philip R.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1994

fDate

26-29 Apr 1994

Firstpage

268

Lastpage

274

Abstract

IBM´s recently announced Scalable POWERparallel family of systems is based upon the Vulcan architecture, and the currently available 9076 SP1 parallel system utilizes fundamental Vulcan technology. The experimental Vulcan parallel processor is designed to scale to many thousands of microprocessor-based nodes. To support a machine of this size, the nodes and network incorporate a number of unusual features to scale aggregate bandwidth, enhance reliability, diagnose faults, and simplify cabling. The multistage Vulcan network is a unified data and service network driven by a single oscillator. An attempt is made to detect all network errors via cyclic redundancy checking (CRC) and component shadowing. Switching elements contain a dynamically allocated shared buffer for storing blocked packet flits from any input port. This paper describes the key elements of Vulcan´s hardware architecture and implementation details of the Vulcan prototype

Keywords

IBM computers; buffer storage; error detection; fault tolerant computing; multiprocessor interconnection networks; parallel architectures; parallel machines; reliability; storage allocation; 9076 SP1 parallel system; IBM Scalable POWERparallel systems; Vulcan architecture; aggregate bandwidth; blocked packet flits; cabling; component shadowing; cyclic redundancy checking; dynamically allocated shared buffer; fault diagnosis; implementation details; input port; microprocessor-based nodes; multistage network; network error detection; oscillator driven network; reliability; switching elements; unified data/service network; Aggregates; Bandwidth; Buffer storage; Cyclic redundancy check; Hardware; Oscillators; Packet switching; Process design; Prototypes; Shadow mapping;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing Symposium, 1994. Proceedings., Eighth International

Conference_Location

Cancun

Print_ISBN

0-8186-5602-6

Type

conf

DOI

10.1109/IPPS.1994.288290

Filename

288290