A methodology for efficient design of analog circuits using an automated simulation based synthesis tool

We present a methodology for efficient design of analog circuits using an automated simulation based synthesis tool. In this methodology, the designer chooses a suitable circuit topology and defines the performance criteria of the circuit. The synthesis tool provides optimized device dimensions which guarantees that the circuit meets the specified performance criteria across process corners. This methodology is independent of the circuit type (as long as the performance criteria can be quantified and measured from simulation data), the fabrication process being used, and also the circuit simulator of choice. We show that this design methodology reduces the design cycle time by a significant amount and helps analysing the trade off between different performance criteria. It also helps in analysing the suitability of several alternative topologies for a given purpose in a short time. In this paper we substantiate this claim with the help of an operational amplifier design.