Title :
A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing
Author :
Chang, Chen-Haur ; Lee, Chuan-Yiu ; Chien, Shao-Yi
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A ray-triangle intersection unit design for ray-tracing in embedded systems is fabricated by TSMC 0.13 mum technology. Bounding volume hierarchy data structure is employed to reduce the on-chip memory requirement. Multi-threading technique is used in the traversal unit to improve the hardware utilization and performance. Moreover, the cost of intersection unit is optimized with folding technique and reconfigurable datapath. Furthermore, the memory bandwidth is reduced with the proposed multi-bank cache architecture. It can provide the processing speed of 50 M-intersections/s with only 2.88 mm2 in hardware cost.
Keywords :
microprocessor chips; multi-threading; ray tracing; storage management; TSMC; embedded systems; folding technique; interactive ray tracing; memory bandwidth; multibank cache architecture; multithreading technique; onchip memory requirement; ray-triangle intersection unit; volume hierarchy data structure; Bandwidth; Computer architecture; Computer graphics; Costs; Data structures; Embedded system; Hardware; Layout; Ray tracing; Rendering (computer graphics);
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708758
