DocumentCode
1832999
Title
Implementation of high performance false contour reduction system using pattern analysis and error-predict method for PDP-HDTV
Author
Lee, Honam ; Koichi, Sono ; Cho, Bonghwang ; Lee, Taeyoung ; Lee, Hoyoung
fYear
2003
fDate
17-19 June 2003
Firstpage
412
Lastpage
413
Abstract
This paper proposes a high performance false contour reduction system with pattern analysis algorithm for PDP-HDTV. It also presents the optimized design and implementation of the method. The proposed method is verified using the Xilinx. Virtex-II FPGA XC2V2000-BG575. Furthermore, we suggest an advanced error-prediction algorithm for high performance. This method is demonstrated experimentally for a 50" PDP-HDTV.
Keywords
field programmable gate arrays; flat panel displays; high definition television; optimisation; plasma displays; television receivers; 50 inch; PDP-HDTV; Virtex-II FPGA XC2V2000-BG575; Xilinx; error-predict method; error-prediction algorithm; high performance false contour reduction system; optimized design; pattern analysis algorithm; Algorithm design and analysis; Consumer electronics; Field programmable gate arrays; HDTV; Image quality; Motion detection; Pattern analysis; Plasma displays; Prediction algorithms; SONOS devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2003. ICCE. 2003 IEEE International Conference on
Print_ISBN
0-7803-7721-4
Type
conf
DOI
10.1109/ICCE.2003.1218997
Filename
1218997
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