Title :
A 15–20GHz delay-locked loop in 90nm CMOS technology
Author :
Chang, Jung-Yu ; Chuang, Chi-Nan ; Liu, Shen-Iuan
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.
Keywords :
CMOS integrated circuits; MMIC; delay lines; delay lock loops; jitter; CMOS technology; DLL; delay-locked loop; frequency 15 GHz to 20 GHz; peak-to-peak jitters; power 49 mW; power consumption; root-mean-square jitters; size 90 micron; voltage 0.9 V; voltage-controlled delay line; CMOS technology; Circuits; Clocks; Delay lines; Energy consumption; Jitter; Phase detection; Phase frequency detector; Power harmonic filters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708766
