DocumentCode :
1833113
Title :
A single-chip hybrid media processor for CRT and matrix displays-based televisions
Author :
Rathnam, Selliah ; Slavenburg, Gerrit ; Nayak, Sheethal ; Bellers, Erwin ; Janssen, Johan
Author_Institution :
Philips Semicond., Sunnyvale, CA, USA
fYear :
2003
fDate :
17-19 June 2003
Firstpage :
418
Lastpage :
419
Abstract :
The new generation of CRT or matrix displays-based television requires high quality video, audio and graphics processing at a lower cost. When available, such a media processing system will drive the wide spread usage of high performance television. A single chip hybrid (analog/digital) TV media processor is designed to implement high quality television at a lower cost.
Keywords :
audio signal processing; computer graphics; digital signal processing chips; television picture tubes; television receivers; video signal processing; CRT; audio processing; digital signal processing CPU; digital video decoding; graphics processing; high performance television; matrix display; media processing; single-chip hybrid media processor; television; video enhancement; video processing; Cathode ray tubes; Decoding; Digital signal processing; Graphics; Hardware; Noise reduction; Read-write memory; Streaming media; TV; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, 2003. ICCE. 2003 IEEE International Conference on
Print_ISBN :
0-7803-7721-4
Type :
conf
DOI :
10.1109/ICCE.2003.1219001
Filename :
1219001
Link To Document :
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