• DocumentCode
    1833123
  • Title

    A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture

  • Author

    Kuroda, Naoki ; Yamada, Naoki ; Nakamura, Toshihiro ; Sumimoto, Yoshihiko ; Hirose, Masanobu ; Ohta, Kiyoto ; Agata, Yasuhiro ; Yamasaki, Yuji ; Akamatsu, Hironori

  • Author_Institution
    Semicond. Co., Matsushita Electr. Ind. Co., Ltd., Nagaokakyo
  • fYear
    2008
  • fDate
    3-5 Nov. 2008
  • Firstpage
    233
  • Lastpage
    236
  • Abstract
    The SRAM-interface High-speed DRAM (SH-RAM) is an embedded DRAM that can replace almost all embedded SRAMs in SoC fabricated by a 65-nm LSTP embedded DRAM process. This paper describes the SH-RAM compiler that realizes a 1.8-ns random cycle time and a 1.5-ns random access time at 512-Kb macro without area penalty by High-speed Bit Line Operation and Data Line Replica Architecture.
  • Keywords
    DRAM chips; SRAM chips; system-on-chip; High-speed Bit Line Operation; SoC; data line replica architecture; random cycle SRAM-interface high-speed DRAM; size 65 nm; time 1.5 ns; time 1.8 ns; Capacitance; Circuits; Costs; Couplings; Data communication; MOSFETs; Noise figure; Power supplies; Random access memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
  • Conference_Location
    Fukuoka
  • Print_ISBN
    978-1-4244-2604-1
  • Electronic_ISBN
    978-1-4244-2605-8
  • Type

    conf

  • DOI
    10.1109/ASSCC.2008.4708771
  • Filename
    4708771
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1833123