A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920times1080 pixels at 30 fps which haven´t been realized by conventional methods. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation- free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5times2.5 mm². With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.