• DocumentCode
    1833270
  • Title

    A 500-MHz MRAM macro for high-performance SoCs

  • Author

    Sakimura, Noboru ; Nebashi, Ryusuke ; Honjo, Hiroaki ; Saito, Shinsaku ; Kato, Yuko ; Sugibayashi, Tadahiko

  • Author_Institution
    Device Platforms Labs., NEC Corp., Sagamihara
  • fYear
    2008
  • fDate
    3-5 Nov. 2008
  • Firstpage
    261
  • Lastpage
    264
  • Abstract
    A 500-MHz MRAM macro is developed using a 0.15-mum CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-mum2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TIMTJ-cell-based MRAM macro in SoCs.
  • Keywords
    CMOS memory circuits; MRAM devices; UHF integrated circuits; system-on-chip; 5T2MTJ; CMOS process; MRAM macro; frequency 500 MHz; hierarchically-divided read bit line; high-performance SoC; magnetic tunnel junction; pre-charge sensing scheme; size 0.15 mum; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
  • Conference_Location
    Fukuoka
  • Print_ISBN
    978-1-4244-2604-1
  • Electronic_ISBN
    978-1-4244-2605-8
  • Type

    conf

  • DOI
    10.1109/ASSCC.2008.4708778
  • Filename
    4708778
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1833270