DocumentCode
1833406
Title
A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications
Author
Ickes, Nathan ; Finchelstein, Daniel ; Chandrakasan, Anantha P.
Author_Institution
Massachusetts Inst. of Technol., Cambridge, MA
fYear
2008
fDate
3-5 Nov. 2008
Firstpage
289
Lastpage
292
Abstract
We describe a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 muW (10 pJ per instruction). Architectural optimizations for energy efficiency include a custom CPU instruction set, miniature instruction cache, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory.
Keywords
acoustic signal detection; cache storage; digital signal processing chips; microprocessor chips; microsensors; 4-MIPS micropower DSP; CPU instruction set; FFT operations; FIR filter; acoustic sensing; energy efficiency; extensive power gating; hardware accelerator cores; medium bandwidth microsensor applications; miniature instruction cache; power 40 muW; sensor applications; Clocks; Decoding; Digital signal processing; Digital signal processing chips; Finite impulse response filter; Logic; Optimal control; Pipelines; Read-write memory; Size control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location
Fukuoka
Print_ISBN
978-1-4244-2604-1
Electronic_ISBN
978-1-4244-2605-8
Type
conf
DOI
10.1109/ASSCC.2008.4708784
Filename
4708784
Link To Document