• DocumentCode
    1833446
  • Title

    Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

  • Author

    Saifhashemi, A. ; Pedram, H.

  • Author_Institution
    Dept. of Comput. Eng., Amirkabir Univ. of Technol., Tehran, Iran
  • fYear
    2003
  • fDate
    2-6 June 2003
  • Firstpage
    330
  • Lastpage
    333
  • Abstract
    In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.
  • Keywords
    asynchronous circuits; hardware description languages; logic design; modelling; programming languages; CSP; PLI; Verilog HDL; behavioral level; communicating sequential processes; programming language interface; synchronous circuits modeling; Asynchronous circuits; Circuit simulation; Cogeneration; Computer languages; Concurrent computing; Hardware design languages; Logic design; Logic programming; Parallel programming; Permission;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2003. Proceedings
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    1-58113-688-9
  • Type

    conf

  • DOI
    10.1109/DAC.2003.1219018
  • Filename
    1219018
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1833446