DocumentCode :
1833462
Title :
On-chip logic minimization
Author :
Lysecky, Roman ; Vahid, Frank
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
fYear :
2003
fDate :
2-6 June 2003
Firstpage :
334
Lastpage :
337
Abstract :
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such as Internet Protocol routing table and network access control list reduction, require logic minimization during the application´s runtime, and hence could benefit from minimization executing on-chip alongside the application. On-chip minimization can even enable dynamic hardware/software partitioning. We discuss requirements of on-chip logic minimization, and present our new on-chip logic minimization tool, ROCM. We compare with the well-known Espresso logic minimizer and show that ROCM is 10 times smaller, executes 10-20 times faster, and uses 3 times less data memory, with a mere 2% quality penalty, for the routing table and access control list applications. We show that ROCM solves real-sized problems on an ARM7 embedded processor in just seconds.
Keywords :
embedded systems; logic design; minimisation of switching nets; system-on-chip; ARM7 embedded processor; Internet Protocol; Riverside on-chip minimizer; control list reduction; data memory; dynamic hardware partitioning; dynamic optimization; dynamic software partitioning; embedded systems; network access; on-chip logic minimization; routing table; system-on-a-chip; Access control; Access protocols; Application software; Boolean functions; IP networks; Logic; Minimization methods; Network synthesis; Routing protocols; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
Type :
conf
DOI :
10.1109/DAC.2003.1219019
Filename :
1219019
Link To Document :
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