Title :
A framework for evaluating test pattern generation strategies
Author_Institution :
Dept. of Comput. Sci., Stanford Univ., CA, USA
Abstract :
A formal approach for the analysis of heuristics used in automatic test pattern generation for combinational circuits is presented. A test pattern generation system that constructs a satisfying assignment for a Boolean formula describing the legal set of tests is discussed. Heuristics as modifications to the formula or the satisfier acting on the formula are described. Experimental results are provided for the system as a whole, and for the effects of four heuristics
Keywords :
Boolean functions; automatic testing; combinatorial circuits; logic testing; Boolean formula; automatic test pattern generation; combinational circuits; heuristics; test pattern generation strategies; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Law; Legal factors; Legged locomotion; System testing; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63325
