Analysis of CORDIC-based triangularization for MIMO MMSE filtering

In this paper, hardware implementation of a 4 times 4 MIMO MMSE Equalizer based on a matrix triangularization is analysed. An architecture is proposed, where the 81 rotations required in the triangularization process are performed using pipelined CORDIC. Based on this architecture, the trade-off between complexity and data rate is studied through two FPGA implementations of the MMSE equalizer, computing MMSE filtering every 6 clock cycles or 38 clock cycles. Hardware complexity evaluations shows that due to the irregular computational need of the triangularization, it is more efficient to pipeline operations as much as possible to obtain the best complexity/data rate trade-off.