An effective capacitance based driver output model for on-chip RLC interconnects

This paper presents a new library compatible approach to gate-level timing characterization in the presence of RLC interconnecting loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources. It is compatible with existing library characterization methods and is computationally efficient. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate.