A programmable-bandwidth front-end with clock-interleaving down-conversion filters

Author

Huang, Ming-Feng ; Chen, Lai-Fu

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

349

Lastpage

352

Abstract

Integration of a programmable-bandwidth front-end (PBFE) based on clock-interleaving down-conversion filter (CIDCF) is presented. After demonstration, PBFE has a programmable bandwidth from 1-MHz to 110-MHz. Under 6.14-mA power current (excluding output buffer) and 1.2-V power supply, PBFE gets +8.2-dBm IIP₃, +45-dBm IIP₂, and 2.6-dB gain. Moreover, a better than 26.79-dB alias-band rejection and 34.032-dB image rejection ratio are obtained. Using a 64-QAM signal with 54-MS/s for IEEE 802.11g standard, PBFE achieves -26.351-dB EVM on a 2.412-GHz RF frequency, 1.072-GHz LO frequency, and 1072-MS/s sampling frequency.

Keywords

CMOS integrated circuits; UHF filters; UHF oscillators; quadrature amplitude modulation; wireless LAN; 12-4 CMOS process; 64-QAM signal; IEEE 802.11g standard; alias-band rejection ratio; clock-interleaving down-conversion filters; current 6.14 mA; frequency 1 MHz to 110 MHz; frequency 1.072 GHz; frequency 2.412 GHz; gain 2.6 dB; image rejection ratio; programmable-bandwidth front-end; sampling frequency; voltage 1.2 V; Attenuation; Band pass filters; Bandwidth; Circuits; Clocks; Finite impulse response filter; IIR filters; RF signals; Radio frequency; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708799

Filename

4708799