DocumentCode :
1833815
Title :
A single-chip UMTS receiver with integrated digital frontend in 0.13 μm CMOS
Author :
Zipper, Josef ; Hueber, Gernot ; Holm, Andreas
Author_Institution :
Danube Integrated Circuits Eng., Linz
fYear :
2008
fDate :
18-21 May 2008
Firstpage :
972
Lastpage :
975
Abstract :
A single-chip zero-IF UMTS receiver for the band classes I, II, and V is presented. The mixed-signal receiver comprises in the analog front-end two self-matched LNAs, an I/Q-mixer, and a fully-integrated DeltaSigma-fractional-N PLL with VCO. Hence, minimum external component count is achieved. The I/Q-ADCs and a digital front-end (DFE) located on the same die enables a shift of signal processing formerly performed in the analog front-end into preferred digital domain. The DFE´s functionality mainly includes sample-rate conversion, channel filtering, dynamic range control and matched filtering. Through a high-speed digital serial interface the received and down-converted signal is finally further transmitted to the baseband IC. The presented RFIC, which is controlled via an integrated three-wire-bus interface, is realized in a 0.13 mum RF- CMOS process and occupies a die size of 8 mm . Measured key figures of merit show an NF of 7.8 dB at 48 dB gain of the analog part in band V and a maximum error-vector-magnitude (EVM) of 3.9%.
Keywords :
3G mobile communication; CMOS digital integrated circuits; low noise amplifiers; mixed analogue-digital integrated circuits; mixers (circuits); phase locked loops; radio receivers; radiofrequency integrated circuits; voltage-controlled oscillators; CMOS integrated circuit; DeltaSigma-fractional-N PLL; I/Q-ADC; I/Q-mixer; RFIC; VCO; digital front-end; gain 48 dB; high-speed digital serial interface; integrated digital frontend; low noise amplifer; mixed-signal receiver; noise figure 7.8 dB; phase locked loops; signal processing; single-chip UMTS receiver; size 0.13 mum; voltage controlled oscillators; 3G mobile communication; Baseband; CMOS integrated circuits; Digital signal processing; Dynamic range; Filtering; Matched filters; Phase locked loops; Signal processing; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
Type :
conf
DOI :
10.1109/ISCAS.2008.4541582
Filename :
4541582
Link To Document :
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