Analysis and modeling verification for thermal-mechanical deformation in flip-chip packages

Plastic flip-chip packaging provides a high-performance and low-cost approach for development of electronic packages. The underfill material plays a key role in enhancing shear fatigue reliability of the solder bump interconnection between the chip and the substrate. However, it raises another reliability concern for delamination at the chip/underfill and the underfill/substrate interfaces. This paper focuses on the driving force of the delamination by investigating the stress distribution at the chip/underfill and the underfill/substrate interfaces. An in-situ moire interferometry technique was used to measure the thermal deformation in the interface areas of an underfilled flip-chip-on-board package. Finite element analysis (FEA) and an analytical solution based on the built-up-bar (BUB) theory were performed to examine the localized stress distribution under thermal loading. The correlation between the experimental and modeling results is discussed. The use of BUB analysis to examine the effect of material properties on stress and deformation of multilayered packages is also discussed