Title :
A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage
Author :
Wang, I-Hsin ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A four-bit 10 GSample/sec flash analog-to-digital converter (ADC) with merged interpolation and reference voltage is presented. In this flash ADC, two clock-gated interpolation amplifiers are adopted and the number of resistor strings is reduced. An on-chip phase-locked loop is integrated to double sample the input signal and down sample the converted digital outputs, respectively. Furthermore, a digital-to-analog converter is embedded for the sake of measurements. This chip has been fabricated in 0.13 mum CMOS process and the ADCpsilas power consumption is 115 mW for a 1.2 V supply voltage. This ADC achieves the SNDR of 25 dB, INL of plusmn0.25 LSB, and DNL of plusmn0.5 LSB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; phase locked loops; CMOS process; clock-gated interpolation amplifiers; flash analog-to-digital converter; merged interpolation; on-chip phase-locked loop; power 155 mW; reference voltage; resistor strings; size 0.13 mum; storage capacity 4 bit; voltage 1.2 V; Analog-digital conversion; CMOS process; Clocks; Digital-analog conversion; Energy consumption; Interpolation; Phase locked loops; Resistors; Semiconductor device measurement; Voltage; Analog-digital converter; digital-to-analog converter; interpolation; phase-locked loop;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708806
