Study of Cu contamination during copper integration in a dual damascene architecture for sub-quarter micron technology

Author

Torres, J. ; Palleau, J. ; Motte, P. ; Tardif, F. ; Bernard, H.

Author_Institution

CNET, Meylan, France

fYear

1998

fDate

1-3 Jun 1998

Firstpage

232

Lastpage

234

Abstract

A detailed study of the copper contaminating step was performed during the integration of Cu metallization in a dual damascene architecture for sub-quarter micron CMOS technology. Dielectric deposition on copper was shown to be critical for SiO₂ contamination. Both the SiO₂ insulator and the etch-stop layer surface can be efficiently cleaned by using dilute HF before subsequent processing. However, this solution was shown not to be effective with inorganic antireflective coatings used for line level photolithography, which are contaminated during chemical mechanical polishing, so a complete removal of this film should be performed during integration

Keywords

CMOS integrated circuits; antireflection coatings; chemical mechanical polishing; copper; dielectric thin films; etching; integrated circuit interconnections; integrated circuit metallisation; photolithography; surface contamination; 0.25 micron; ARC film removal; CMOS technology; Cu contamination; Cu metallization; Cu-SiO₂; HF; SiO₂ contamination; SiO₂ insulator; chemical mechanical polishing; copper contaminating step; copper integration; dielectric deposition; dilute HF cleaning; dual damascene architecture; etch-stop layer surface; inorganic antireflective coatings; line level photolithography; CMOS technology; Coatings; Copper; Dielectrics and electrical insulation; Etching; Hafnium; Inorganic chemicals; Lithography; Metallization; Surface contamination;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704908

Filename

704908