Two bit-level pipelined viterbi decoder for high-performance UWB applications

This paper presents a high-speed low-complexity two bit-level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes two bit-level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques, to reduce a critical path of the ACSU. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V. It operates at a clock frequency of 870 MHz and has a throughput of 1.74 Gb/s.