Automatic trace analysis for logic of constraints

Author

Chen, Xi ; Hsieh, Harry ; Balarin, Felice ; Watanabe, Yosinori

Author_Institution

California Univ., Riverside, CA, USA

fYear

2003

fDate

2-6 June 2003

Firstpage

460

Lastpage

465

Abstract

Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simulation traces for functional and performance constraint violations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We illustrate the usefulness and efficiency of this approach with large designs and traces.

Keywords

constraint handling; digital simulation; performance evaluation; program verification; automatic trace analysis; linear time complexity; logic of constraints; memory usage; performance constraint; quantitative constraint language; simulation checker; system verification; trace checkers; Analytical models; Automatic logic units; Embedded system; Formal verification; Lab-on-a-chip; Logic design; Performance analysis; Permission; Signal processing algorithms; System analysis and design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219045

Filename

1219045