Title :
On-chip clock network skew measurement using sub-sampling
Author :
Das, Pratap Kumar ; Amrutur, Bharadwaj ; Sridhar, J. ; Visvanathan, V.
Author_Institution :
ECE Dept., Indian Inst. of Sci., Bangalore
Abstract :
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5 ps and a DNL of 1.2 ps.
Keywords :
clocks; delay circuits; digital integrated circuits; all-digital on-chip delay measurement system; clock distribution network; industrial process; skew measurement; sub-sampling; Clocks; Delay; Detectors; Network-on-a-chip; Phase detection; Sampling methods; Semiconductor device measurement; Signal resolution; System-on-a-chip; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708812
