DocumentCode
1834406
Title
An 833-MHz 132-phase multiphase clock generator with self-calibration circuits
Author
Lin, Shih-Chun ; Lee, Tai-Cheng
Author_Institution
Dept. of Electr. Eng. & Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
fYear
2008
fDate
3-5 Nov. 2008
Firstpage
437
Lastpage
440
Abstract
An 833-MHz 132-phase clock generator with self-calibrated circuits is presented. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phases is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-mum CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply.
Keywords
CMOS integrated circuits; UHF devices; UHF generation; calibration; charge pump circuits; delay lock loops; phase locked loops; signal generators; CMOS technology; DLL calibration algorithm; calibration circuits; charge pump; delay-locked loops; frequency 833 MHz; multiphase clock generator; phase detector; power 67.2 mW; self-calibration circuits; sequential comparison method; size 0.13 mum; voltage 1.2 V; CMOS technology; Calibration; Charge pumps; Circuits; Clocks; Delay; Detectors; Phase detection; Power generation; Power supplies;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location
Fukuoka
Print_ISBN
978-1-4244-2604-1
Electronic_ISBN
978-1-4244-2605-8
Type
conf
DOI
10.1109/ASSCC.2008.4708821
Filename
4708821
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