DocumentCode :
1834741
Title :
Clock-tree power optimization based on RTL clock-gating
Author :
Donno, Monica ; Ivaldi, Alessandro ; Benini, Luca ; Macii, Enrico
Author_Institution :
BullDAST SRL, Torino, Italy
fYear :
2003
fDate :
2-6 June 2003
Firstpage :
622
Lastpage :
627
Abstract :
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing clock power based on clock gating. We present a methodology that, starting from an RTL description, automatically generates a set of constraints for driving the construction of the clock tree by the clock synthesis tool. The methodology has been fully integrated into an industry-strength design flow, based on Synopsys DesignCompiler (front-end) and Cadence Silicon Ensemble (back-end). The power savings achieved on some industrial examples show that, when the size of the circuits is significant, savings on the power consumption of the clock tree are up to 75% larger than those achieved by applying traditional clock gating at the clock inputs of the RTL modules of the designs.
Keywords :
clocks; low-power electronics; optimisation; RTL clock-gating; clock synthesis tool; clock-tree power optimization; low-power design; power saving; Circuits; Clocks; Construction industry; Energy consumption; Flip-flops; Hardware; Network synthesis; Permission; Power measurement; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
Type :
conf
DOI :
10.1109/DAC.2003.1219093
Filename :
1219093
Link To Document :
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