A case study of RC effects to circuit performance

The contributing RC time delay from metal interconnects, which is approaching or even exceeding the gate delay at the transistor level, becomes an issue for high speed VLSI applications. The capacitance issue can be more severe in RC effects due to the fact that metal height can not be scaled down at the same pace as the metal width or spacing (due to reliability concerns). As a result, process developments for a low dielectric constant (low k) material suitable for multilevel interconnect VLSI applications have drawn a great deal of attention. We have studied RC effects by first comparing the effective capacitance from simulations using various dielectric structures. Then, an ASIC benchmark testing circuit (divide-by-three counter) is used to investigate the significance of these dielectric structures to the circuit performance. Finally, we have looked into details of the interconnect length and design rule effects on circuit performance by increasing the interconnect length between the gates of the divide-by-three counter. Although the circuit itself is simple and is not optimized for high performance, this exercise does reveal the significance of the RC effects. With better understanding of the roles of RC and layout in circuit performance, the advantages of copper/low k interconnects can be better realized