Title :
Using satisfiability in application-dependent testing of FPGA interconnects
Author :
Tahoori, Mehdi Baradaran
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
In this paper, a new technique for testing the interconnects of an arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed. The test vector and configuration generation problem is systematically converted to a satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list.
Keywords :
computability; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGA interconnect; SAT problem; SAT solver; application-dependent testing; arbitrary design; benchmark circuit; bridging fault; fault coverage; field programmable gate array; logic block; satisfiability problem; test configuration generation; test vector; Application specific integrated circuits; Circuit faults; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Logic testing; Programmable logic arrays; Switches; System testing;
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
DOI :
10.1109/DAC.2003.1219104
