Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

Author

Maneatis, John G. ; Kim, Jaeha ; McClatchie, Iain ; Maxey, Jay ; Shankaradas, Manjusha

Author_Institution

True Circuits, Inc., Los Altos, CA, USA

fYear

2003

fDate

2-6 June 2003

Firstpage

688

Lastpage

690

Abstract

A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13μm CMOS, the area is 0.182mm² and the supply is 1.5V.

Keywords

CMOS digital integrated circuits; clocks; current mirrors; digital filters; frequency multipliers; integrated circuit design; jitter; phase locked loops; 0.13 micron; 1-to-4096 multiplier; 1.5 V; adaptive bandwidth; clock generation; clock generator PLL; clock multiplication; constant loop dynamics; feed-forward filter network; frequency synthesis; high-bandwidth PLL; inverse-linear programmable current mirror; low-jitter PLL; multiplication factor; output frequency; phase locked loop; reference frequency; self-biased PLL; Bandwidth; Clocks; Feedforward systems; Filters; Frequency; Integrated circuit reliability; Jitter; Mirrors; Permission; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219106

Filename

1219106