A 1.3GHz fifth generation SPARC64 microprocessor

Author

Ando, Hisashige ; Yoshida, Yuuji ; Inoue, Aiichiro ; Sugiyama, Ltsumi ; Asakawa, Takeo ; Morita, Kuniki ; Muta, Toshiyuki ; Motokurumada, Tsuyoshi ; Okada, Seishi ; Yamashita, Hideo ; Satsukawa, Yoshihiko ; Konmoto, Akihiko ; Yamashita, Ryouichi ; Sugiyam

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

fYear

2003

fDate

2-6 June 2003

Firstpage

702

Lastpage

705

Abstract

A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 37.4W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools.

Keywords

CMOS integrated circuits; integrated circuit design; microprocessor chips; silicon-on-insulator; 1.3 GHz; 130 nm; 37.4 W; SOI CMOS process; Unix server; chip size; clock distribution; copper metallization; data logic error; data path logic circuit; error detection; execution unit; fifth generation SPARC64 microprocessor; on-chip array; power dissipation; recovery mechanism; silicon-on-insulator; CMOS process; Clocks; Integrated circuit reliability; Laboratories; Logic circuits; Metallization; Microprocessors; Pipelines; Power dissipation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219109

Filename

1219109