Title :
Variability-aware design of subthreshold devices
Author :
Jaramillo-Ramirez, Rodrigo ; Jaffari, Javid ; Anis, Mohab
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON
Abstract :
Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks for digital subthreshold logic circuits. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this paper, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. By using the technique, a process/device designer can optimize a transistor for subthreshold operation in terms of the total leakage current and intrinsic delay bounds. Sample devices are optimized for 90 nm and 65 nm technologies, and Monte Carlo simulations verify the accuracy of the technique.
Keywords :
Monte Carlo methods; circuit optimisation; integrated circuit design; integrated circuit yield; leakage currents; logic circuits; Monte Carlo simulations; construction blocks; digital subthreshold logic circuits; intrinsic delay bounds; leakage current; size 65 nm; size 90 nm; subthreshold devices; subthreshold drive current; subthreshold operation; transistor; variability aware design; yield optimization; Capacitance; Design optimization; Doping profiles; Leakage current; Logic circuits; Logic design; Logic devices; Subthreshold current; Threshold voltage; Tunneling;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541638
