A 1.5GHz third generation Itanium 2 processor

Author

Stinson, Jason ; Rusu, Stefan

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

2003

fDate

2-6 June 2003

Firstpage

706

Lastpage

709

Abstract

This 130nm Itanium® 2 processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6MB, 24-way set associative L3 cache. The 374mm² die contains 410M transistors and is implemented in a dual-Vt process with 6 layers copper interconnect and FSG dielectric. The processor runs at 1.5GHz at 1.3V and dissipates a maximum of 130W. This paper reviews circuit design and package details, power delivery, RAS, DFT and DFM features, as well as an overview of the design and verification methodology. The fuse-based clock de-skew circuit achieves 24ps skew across the entire die, while the scan-based skew control further reduces it to 7ps. The 128-bit front-side bus supports up to 4 processors on a single bus with a bandwidth of up to 6.4GB/s.

Keywords

cache storage; integrated circuit design; integrated circuit packaging; microprocessor chips; parallel architectures; 1.3 V; 1.5 GHz; 128 bits; 130 W; 130 nm; 6.4 Gbits/s; DFM feature; DFT; EPIC architecture; FSG dielectric; Itanium 2 processor; RAS; circuit design; copper interconnect; design methodology; dual-Vt process; explicitly parallel instruction computing; fluorinated silica glass; fuse-based clock de-skew circuit; on-die cache; power delivery; scan-based skew control; verification methodology; Circuit synthesis; Computer aided instruction; Computer architecture; Concurrent computing; Copper; Design for manufacture; Design methodology; Dielectrics; Integrated circuit interconnections; Packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219110

Filename

1219110