FSMD partitioning for low power using simulated annealing

It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique which uses simulated annealing to efficiently partition a FSMD for power gating. We use this non-linear model to partition 4 application circuits. We then develop a framework to estimate the potential power savings. The estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.